Quicksilver is a 2D accelerator implemented using SystemVerilog. It is designed to plug into existing SoCs via the APB bus. A small graphics library was also developed for the accelerator to ease the programming burden. This design has been integrated into a past chip designed by Purdue’s SoC team and the functionality of the accelerator and C library have been verified on an FPGA implementation of the SoC.
The above .gif was generated using only the accelerator’s primitives via a mapped simulation of Quicksilver, using 24 bit color at a 640 x 480 resolution. 32 frames were rendered at 125 frames per second.
A link to the Github repository associated with this project can be found here