Jacob R. Stevens

Ross Fellow, Integrated Systems Lab

Purdue University

Biography

My name is Jacob Stevens. I am a PhD student working in Purdue’s Integrated Systems Lab under Dr. Anand Raghunathan.

Interests

System on Chip Design
Neuromorphic Computing
Machine Learning

Education

PhD in Computer Engineering, ongoing

Purdue University
BSc in Computer Engineering, 2016

Purdue University

Selected Publications

AxBA: An Approximate Bus Architecture

The exponential growth in creation and consumption of various forms of digital data has led to the emergence of new application workloads such as machine learning, data analytics and search. These workloads process large amounts of data and hence pose increased demands on the on-chip and off-chip interconnects of modern computing systems. Therefore, techniques that can improve the energy-efficiency and performance of interconnects are becoming increasingly important.

Jacob R. Stevens, Ashish Ranjan, Anand Raghunathan

In ICCAD 2018

Details

ACCLIB: Accelerators as Libraries

In this work, we explore ACCLIB, a design framework aimed at improving the ease with which software developers can utilize libraries of existing hardware accelerators, without detailed prior knowledge of the fuction of the accelerators, or even of hardware design more broadly.

Jacob R. Stevens, Yue Du, Vivek Kozhikkott, Anand Raghunathan

In DATE 2018

Details

Recent Publications

AxBA: An Approximate Bus Architecture
Details
ACCLIB: Accelerators as Libraries
Details
Energy-Aware Memory Mapping for Hybrid FRAM-SRAM MCUs in Intermittently-Powered IoT Devices
Details

Recent Talks

Purdue MicroBrewer: A Microcontroller Generator

Purdue Microbrewer quickly and easily generates various RISCV-powered microcontrollers from an XML configuration file and a library of peripherals, providing the configured RTL, drivers, documentation, and scripts for FPGA synthesis.

RISCV International Conference 2017

Details Slides

RISC-V Business: A Configurable, Extensible RISC-V Core

RISCV-Business is an open source project aimed at creating a configurable, extendable RISC-V core for university researchers and those trying to learn about computer architecture through a hands on approach.